--- Quote Start ---
Why are you using integers in your code?
buffRot is std_logic_vector(31 downto 0), so UNSIGNED(buffRot) is a 32-bit unsigned value, and you cannot convert that to a 32-bit (signed) integer.
VHDL Specification (5.2.3.2 Predefined integer types):
"The only predefined integer type is the type INTEGER. The range of INTEGER is implementation dependent, but it is guaranteed to include the range –2147483647 to +2147483647. It is defined with an
ascending range."
i.e., integers have a guaranteed range of up to 0x7FFF_FFFF, which is a 31-bit unsigned number.
Your code:
subSubRot <= STD_LOGIC_VECTOR(TO_UNSIGNED(TO_INTEGER(UNSIGNED(buffRot)) - TO_INTEGER(UNSIGNED(RELATION)),32));
subIncRot <= STD_LOGIC_VECTOR(TO_UNSIGNED(TO_INTEGER(UNSIGNED(buffRot)) + TO_INTEGER(UNSIGNED(RELATION)),32));
should be re-written to use unsigned and/or signed types, the resize() operator, and then an appropriate rounding method.
Cheers,
Dave
--- Quote End ---
Hi Dave,
I think that he is not converting it to any signed but the compiler does and it does lose 1 bit eventually from this 32 bit input.
the input buffrot(30 : 0) is mapped(I believe) to 31:1(i.e. bit 31 dropped) and an extra fixed lsb of 1 is added.
the "relation" input is 23:0 mapped to 24:1 and extra 1 also added so overall a 2 enters adder with inputs then one lsb must be discarded at output so in effect 1 is added(2/2).
So in principle it should work unless the user enters really large value on buffrot.
Thanks
Honored Contributor
