Altera_Forum
Honored Contributor
Honored ContributorAdding nets to signaltap via HDL
Hello, Is it possible to add nets for signaltap debugging using VHDL attributes ?
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Altera_ForumHonored Contributor
Honored ContributorHi,
Do you want attributes to be monitored using signaltap? Hope below links helps you. https://alteraforum.com/forum/showthread.php?t=53741 Refer session 7.1ftp://ftp.altera.com/up/pub/tutorials/de2/digital_logic/tut_signaltapii_vhdlde2.pdf Best Regards, Anand Raj Shankar (This message was posted on behalf of Intel Corporation)
