Honored ContributorHello everybody,
I found the following in the Quartus II user guide: If you would like to tap out the D and Q ports of registers, turn on add d and q ports of register node to simulation output waveform from the Assignment Editor. This feature is only available for functional simulations. But cannot locate this anywhere in the options - has anyone else done this succesfully ? Thanks - Eric
Honored ContributorFrom the Assignments Menu, Select Assignmenst editor to bring up the Assignments editor window.
Under the Assignments Name Column in a new row you can find the "Add D and Q ports of register node to Simulation Output Waveforms" option. You can then apply it to whatever nodes you like. I have to say I have never used this option! the help says "....A logic option that adds the D and Q ports of a register node to the list of signals in the output waveforms that are shown in the Simulation Waveforms section in the Simulation Report after a successful simulation. This option is useful because it makes the D and Q ports of a register node observable during a simulation. The option must be assigned to a register node or it is ignored. This option is available for all Altera devices..." Hope this helps
