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Altera_Forum
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16 years ago

Adding a second PLL to Cyclone III EP3C16

Connecting a PLL to the first input clock (pin 31) compiles OK. But when I try to add a second PLL driven from the second clock pin (pin 32) I get the following error: Error: promoted fro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

Thanks, I can follow that!

Looking at the clock map for the Cyclone 3 (handbook vol 1), it shows PLL1 and PLL3 alongside clock pins 0 to 3 (left hand side). However PLL2 is on the opposite side of the chip (along clocks 4 to 7) right hand side, with no "decent" path from the LHS, so no wonder it wouldn't play ball.

As a test, I created a third PLL, which worked (compensated) OK with clock pin 11 (top side), and also pin 1 (left side).

So now I got a much better feeling of what is going on..

thanks both!