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Altera_Forum
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16 years ago

Adding a second PLL to Cyclone III EP3C16

Connecting a PLL to the first input clock (pin 31) compiles OK. But when I try to add a second PLL driven from the second clock pin (pin 32) I get the following error: Error: promoted fro...
Altera_Forum's avatar
Altera_Forum
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16 years ago

The problem is, because you did not drive your clock to two dedicated clock inputs, that are directly connectable to different PLLs. pin_31 and pin_32 are both dedicated inputs of PLL1.

The good thing is, that starting with Cyclone III (and other high end FPGAs), you are able to route PLL input from non-dedicated pins, chain PLLs and similar. In many designs, it's not absolutely necessary to have the features of dedicated clock inputs, you can accept a somewhat higher jitter and delay tolerance. Clearly, it's not always wanted to connect the clock at opposite sides of the FPGA, as it is required to connect both PLLs directly.