Adding a second PLL to Cyclone III EP3C16

Note that this doesn't "fix" the problem per se. The original warning was that you put the PLL in Normal compensation mode, where it's compensating for the clock delay. But since the PLL is not fed by its dedicated clock(and hence there's a long route from the pin it comes in on to the PLL that is not compensated for), it can't do this "Normal Compensation" that you're asking for. It's still compensating for a lot of the clock path, just not all of it.

By changing the compensation mode to No Compensation, you're not asking for any compensation. Since you're not asking for it, there's no reason to warn you that it wasn't able to do it. But I believe the PLL is still being placed away from the pin driving it and will have a long delay. In fact, it will be considerably longer now. It's generally a better solution to put it back to Normal Compensation, so at least some of it is compensated for and accept that you get a warning, rather than No Compensation.

(Most importantly, compensation basically shifts your clock back in time to compensate for the clock tree delay, i.e. it makes your clock tree seem like it's really fast. This is good for getting quick Tcos and things like that. In essence, it changes the relationship to other domains. If you have timing constraints that are correct, then this whole PLL compensation thing is a secondary affect. If you meet timing wth No Compensation, then everything's fine and you don't have to worry about it. If you do Normal Compensation and your PLL is placed away from the clock pin, but you still make timing, then everything is fine. The reason this is a critical warning is that users often layout their boards before doing timing constraints, and may not be aware that the PLL can't be placed next the clock pin that drives it for whatever reason. They get their boards back, can't meet timing, and can't do anything without a re-spin. BUt if you make timing with it the way it is, then feel free to ignore it...)