Adding 2 32-bit numbers and storing the result in a 33 bit register

p_clock_gen :process
  begin
    clk_128meg_i <= '0';
    
    wait for clk_128meg_i_period/2;
    clk_128meg_i <= '1';
    
    wait for clk_128meg_i_period/2;
  end process;
 
--stimulus  
  p_stim: process
  begin  
     
    wait for 10 ns;
    reset_n_i <= '1';
    
    wait for clk_128meg_i_period;
    enable_i <= '1';
    fcw_i <= "00000000000000000000000000000000";
    mod_i <= "000000000000000000000000";
  
    wait for 50 ns;
    fcw_i <= "11111001011110010001000101111111";      -- 4185461119
    mod_i <= "110100001101110111010000";       -- 13688272
    
    wait for 50 ns;
    fcw_i <= "10101011010101010101110101010111";      -- 2874498391
    mod_i <= "000101110111011101101011";        -- 1537899 
  
    wait for 50 ns;
    fcw_i <= "11001011101101101110101011011101";      -- 3417762525
    mod_i <= "000000100010110110110110";        -- 142774  
   
    wait for 50 ns;
    fcw_i <= "00101010101010101011010100101001";      -- 715830569
    mod_i <= "101010101011010101010101";        -- 11187541
  
    wait for 50 ns;
    fcw_i <= "11111111111111111111111111111111";       -- 4294967295
    mod_i <= "111111111111111111111111";        -- 16777215
  
    wait for 10 ms; 
    reset_n_i <= '0';
 
    wait for 1 ms;
    reset_n_i <= '1';
    wait for 1 ms;
    enable_i <= '0';
    
    wait for 1 ms;
    enable_i <= '1';
    
    wait for 1 ms;
    assert false report " End of the simulation" severity Failure;
  end process;
  
  new_mod_s <= std_logic_vector("000000" & mod_i & "000");
  old_fcw_s <= std_logic_vector("0" & fcw_i);
  delay_rst_s <= reset_n_i after 1 ns;
  
  
  p_fcw_chk: process(delay_rst_s, clk_128meg_i)
  begin
    if (delay_rst_s = '0') then
      assert fcw_mod_o = "000000000000000000000000000000000" report "Output is not set to default value when reset_n_i is 0" severity error;
    elsif (clk_128meg_i'event and clk_128meg_i = '0') then
      if (enable_i = '1') then
    assert fcw_mod_o = std_logic_vector(unsigned(old_fcw_s) + unsigned(new_mod_s)) report "Wrong output" severity error;
      else
        assert fcw_mod_o = "000000000000000000000000000000000" report "Output is not set to default value when enable_i is 0" severity error;
      end if;
   end if;
  end process;
  

Sory I don't get it. Are you trying to check your design or the testbench. Where is the design?

the design code is here:

entity add1 is
    port (reset_n_i : in std_logic;     -- global reset
      clk_128meg_i : in std_logic;  -- 128MHz system clock
      enable_i : in std_logic;      -- global enable
      fcw_i : in std_logic_vector(31 downto 0);   -- fractional number with 4 integer bits from MSB and 28 fractional bits (32 bit width)
      mod_i : in std_logic_vector(23 downto 0);   -- 24 bit fractional number 
      fcw_mod_o : out std_logic_vector(32 downto 0)  -- fcw_i+(5 zeros & mod_i & 3 zeros)
      ); 
end add1;
architecture rtl of add1 is
signal temp_s : std_logic_vector(32 downto 0);   -- Register to store the concatenated mod_i value
signal mod_s : std_logic_vector(32 downto 0);     -- Register to store the added output (fcw_i+temp_s)
signal fcw_s : std_logic_vector(32 downto 0);     -- Register to store the added output (fcw_i)
begin
  p_add1 : process( reset_n_i, clk_128meg_i)
  begin
    if (reset_n_i = '0') then
      mod_s <= (others => '0');
    elsif (clk_128meg_i'event and clk_128meg_i = '1') then
      if (enable_i = '1') then
       mod_s <= std_logic_vector(unsigned(fcw_s) + unsigned(temp_s));  -- Adding of fcw_i and temp_s results in mod_s
      else
    mod_s <= (others => '0');
      end if;
    end if;
  end process;
  fcw_s <= std_logic_vector("0" & fcw_i);   -- Five zeros are appended to the MSB of mod_i and three zeros are appended to the LSB of mod_i
  temp_s <= std_logic_vector("000000" & mod_i & "000");   -- Five zeros are appended to the MSB of mod_i and three zeros are appended to the LSB of mod_i
  fcw_mod_o <= std_logic_vector(mod_s);            
end rtl;

the design code is here:

entity add1 is
    port (reset_n_i : in std_logic;     -- global reset
	  clk_128meg_i : in std_logic;  -- 128MHz system clock
	  enable_i : in std_logic;      -- global enable
	  fcw_i : in std_logic_vector(31 downto 0);   -- fractional number with 4 integer bits from MSB and 28 fractional bits (32 bit width)
	  mod_i : in std_logic_vector(23 downto 0);   -- 24 bit fractional number 
	  fcw_mod_o : out std_logic_vector(32 downto 0)  -- fcw_i+(5 zeros & mod_i & 3 zeros)
	  ); 
end add1;
architecture rtl of add1 is
signal temp_s : std_logic_vector(32 downto 0);   -- Register to store the concatenated mod_i value
signal mod_s : std_logic_vector(32 downto 0);	 -- Register to store the added output (fcw_i+temp_s)
signal fcw_s : std_logic_vector(32 downto 0);	 -- Register to store the added output (fcw_i)
begin
  p_add1 : process( reset_n_i, clk_128meg_i)
  begin
    if (reset_n_i = '0') then
      mod_s <= (others => '0');
    elsif (clk_128meg_i'event and clk_128meg_i = '1') then
      if (enable_i = '1') then
       mod_s <= std_logic_vector(unsigned(fcw_s) + unsigned(temp_s));  -- Adding of fcw_i and temp_s results in mod_s
      else
	mod_s <= (others => '0');
      end if;
    end if;
  end process;
  fcw_s <= std_logic_vector("0" & fcw_i);   -- Five zeros are appended to the MSB of mod_i and three zeros are appended to the LSB of mod_i
  temp_s <= std_logic_vector("000000" & mod_i & "000");   -- Five zeros are appended to the MSB of mod_i and three zeros are appended to the LSB of mod_i
  fcw_mod_o <= std_logic_vector(mod_s);			
end rtl;

so is your question why when enable is '0' the value of mod_s doesn't default zero?

yes, exactly

There is nothing wrong with adder logic.

Ok, got it. How to write some randomized inputs for this testbench a kind of a loop I mean