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jlanier's avatar
jlanier
Icon for New Contributor rankNew Contributor
5 years ago

Add ROM in Platform Designer and read from ROM with C code and Nios II Processor

I have gone through the Using Triple-Speed Ethernet on DE2-115 Boards tutorial successfully. The tutorial uses a C program with the Nios II processor to send user input data over UART to the FPGA. When the FPGA recieves that data it broadcasts it over Ethernet.

I would now like to send data from a ROM block instead of data received over UART. I am trying to add the ROM block in Platform Designer and I am having trouble with connections.

I am unsure if my issue is the connections in Platform Designer or the way I am trying to read from the ROM in the C program. I have attached the original Platform designer and modified Platform Designer as well as the original C code and my modified C code and the tutorial instructions.

My additions to the modified C code begin on line 135.

Any help would be greatly appreciated!

3 Replies

  • AKb's avatar
    AKb
    Icon for Occasional Contributor rankOccasional Contributor
    5 years ago

    Hi,

    I am trying to implement triple speed ethernet in Cyclone 10 FPGA. I have integrated triple speed ethernet core in platform designer in qsys. If i pump data and do loop back in system side of MAC, its working fine. I am able to monitor Start of packet, data valid, data, End of packet properly in signal tap. Now my aim is that i try to capture the streaming data in system side of MAC directly in Nios side memory. For this i am using Modular Scatter gather DMA. For receive data i am using one MSGDMA in streaming to memory mode and one for transmit data i am using one MSGDMA in memory to streaming mode. I try to capture data in descriptor memory in onchip ram. But i am not getting any data.

    I have doubt about my connections of MSGDMA in Qsys.There are no any specific examples detailing how to use MSGDMA with TSE. Some people have done it with SGDMA . I am using quartus 18.1. So how to go about it. How to capture data in onchip RAM.

    Kindly guide

    Av

  • BoonBengT_Altera's avatar
    BoonBengT_Altera
    Icon for Moderator rankModerator
    5 years ago

    Hi @jlanier

    Thank you for your patients, and hope you are doing well.
    Regarding the question that you have on sending data from ROM block instead fo UART, i believe that is possible, here are a section in the triple speed ethernet user guide that you can refer to:
    https://www.intel.com/content/dam/www/programmable/us/en/pdfs/literature/ug/ug_ethernet.pdf (section 10. Software Programming Interface)

    Also there are other sample design for cyclone device family:
    https://www.intel.com/content/www/us/en/programmable/support/support-resources/design-examples/intellectual-property/embedded/nios-ii/exm-tse-sgdma.html?wapkw=Triple%20Speed%20Ethernet

    Warms Regards

    • BoonBengT_Altera's avatar
      BoonBengT_Altera
      Icon for Moderator rankModerator
      5 years ago

      Hi @jlanier,

      We do not receive any response from you to the previous question that we have provided. Please post a response in the next 15 days to allow me to continue to support you. After 15 days, this thread will be transitioned to community support. The community users will be able to help you with your follow-up questions.

      Warm Regards