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Altera_Forum
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7 years ago

Achieve Low Latency in OpenCL implementation of a State Space Equation Solver

Dear All, I am exploring OpenCL as an alternative to HDL to implement a simple accelerator, to solve state space equations of an Induction Motor, on an FPGA PCIe board. My aim is to have a l...
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Altera_Forum
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7 years ago

Even though I haven't used them myself, many are using System C or System Verilog these days as a higher-productivity alternative to VHDL and Verilog while retaining the low-level control over the pipeline latency.