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Rats, I was hoping there was something to do that. In VHDL, any clocked signal or variable has the next_reg_value (enumerated, integer, std_logic...), even without it being defined, (the next value is routed to the register's 'D' port), it must be determined in advance, before the clock arrives. That VHDL functionality is applicable to any type or manufacturer's hardware, synthesizable or not, like a testbench. Yes it CAN be defined, as shown in the previous demonstration, and requires a different layout, witch I'm trying to avoid.
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VHDL does not have a "next_reg_value" or anything like that. VHDL Has no concept of, or access to, any underlying hardware, whether it's the D port on a latch, the read address of a memory, or a the enable line on a tri-state buffer. Therefore you need to define a signal for ANYTHING you intend to use inside the code. VHDL is a behavioural language. In simulation it works using a series of delta cycles, which are infinitely small periods of time. When a signal assignment occurs, it only schedules the assignment to take place at the end of the current delta cycle, hence why you can make multiple assignments to a signal and only the last one gets assigned (as opposed to variables, which are assigned immediately).
VHDL does have attributes like my_signal'delayed(T) which is a copy of my_signal delayed by time T, but this is a simulation only concept as it would have no meaning in hardware. there is also 'transaction, 'event and 'stable - again, simulation only concepts as they have no meaning in hardware.
For a single process state machine, I just do this:
process(clk)
begin
if rising_edge(clk) then
case state is
when s1 =>
state <= s2;
when s2 =>
state <= s3;
--etc
doing this means you never accidently create any latches, because everything is clocked.
But it will mean some signals may need to be assigned outside of the process if they need to act on the current version of state.
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