Access to Next-Value of Clocked-Value, Without Needin Clocked and Unclocked Processes

Tricky:

Rats, I was hoping there was something to do that. In VHDL, any clocked signal or variable has the next_reg_value (enumerated, integer, std_logic...), even without it being defined, (the next value is routed to the register's 'D' port), it must be determined in advance, before the clock arrives. That VHDL functionality is applicable to any type or manufacturer's hardware, synthesizable or not, like a testbench. Yes it CAN be defined, as shown in the previous demonstration, and requires a different layout, witch I'm trying to avoid.

I used the term <signal name>'attribute since the source value must be accessible by code compilation, and is 100% dependent on the <signal name>, plus logic changes of course, since the signal will hold that value after the clock passes. I searched through as many attribute I could fined, and didn't find anything even close, so I didn't expect it to exist. I guess if I'm the only one who's thought about that, it's unlikely for it to be added to next VHDL version. (I usually stay in '93 version anyway).

What is your state_machine secret for configuration to only have a single clocked process? All four state_machine types in the "Insert Template\VHDL\Full Designs\State Machines" path have both clocked and unclocked processes. I don't really consider the "User-Encoded State Machine" having 2 processes configured the same way, since the clocked process has a single clocked assignment. If there were other clocked outputs dependent on the states, they would need to be added to the clocked process, or their own clocked process, with a case state section witch would promote the process to be viewed as a clocked state process.

Any suggestions I should check out.

David K.