Forum Discussion
Altera_Forum
Honored Contributor
8 years agoIf I understand what you're saying, then the answer is really you are already doing it the way you need to.
This almost feels like the reverse of the problem most newbies have - I think you're visualising your intended circuit in too much detail - VHDL itself has no knowledge of gates and registers - it is the tool that does this conversion. If you really want to get to this level, you can instantiate primitives yourself, but no one else will really want to ever look at your code. So therefore there are no attributes that allow you to access primitive pins, as for some technologies pins may have different names, or not exist at all (remember, VHDL can also map to Xilinx, Atmel, Samsung or any other ASIC vendor primitives, and in theory all from the same code). Try and think behaviour. Having synchronous code and async code is always going to happen. And if your change in behaviour mandates this change, then you have to change the bahaviour of the circuit and hence the code. But have you considered using shorter forms of coding rather than asynchronous processes? something like:
next_counter <= counter + 1 when count_en = '1' else counter;
PS> I never code state machines with 2 processes - always a single clocked process.