About VGA Output

hello,

yes. i am checking that clock in Modelsim Altera starter edition 10.4b version. I have written the test bench program to check the output in modelsim.

test bench code:

LIBRARY IEEE;

USE IEEE.STD_LOGIC_1164.ALL;

USE IEEE.NUMERIC_STD.ALL;

ENTITY VGA_TB IS

END ENTITY VGA_TB;

ARCHITECTURE BEHAVIOUR OF VGA_TB IS

SIGNAL CLOCK_24: STD_LOGIC:= '0';

SIGNAL SYS_rst : STD_LOGIC:= '1';

SIGNAL VGA_HS, VGA_VS: STD_LOGIC:= '0';

SIGNAL VGA_R, VGA_G, VGA_B: STD_LOGIC_VECTOR(7 DOWNTO 0):= (OTHERS => '0');

SIGNAL VGA_CLK_65MHZ : STD_LOGIC:= '0';

COMPONENT VGA IS

PORT (

CLOCK_24: IN STD_LOGIC;

VGA_HS, VGA_VS: OUT STD_LOGIC;

VGA_R, VGA_G, VGA_B: OUT STD_LOGIC_VECTOR(7 DOWNTO 0);

VGA_CLK_65MHZ : OUT STD_LOGIC

);

END COMPONENT;

BEGIN

INST_VGA : VGA

PORT MAP (

CLOCK_24 => CLOCK_24,

VGA_HS => VGA_HS,

VGA_VS => VGA_VS,

VGA_R => VGA_R,

VGA_G => VGA_G,

VGA_B => VGA_B,

VGA_CLK_65MHZ => VGA_CLK_65MHZ);

CLOCK_PROC : PROCESS

BEGIN

CLOCK_24 <= '0';

WAIT FOR 10 NS;

CLOCK_24 <= '1';

WAIT FOR 10 NS;

END PROCESS;

SYS_rst <= '0', '1' AFTER 100 NS;

END;