About timing constraints of ‘in2out’ timing path

I'm sorry for the description fault, the tool calculate the required time is as follows:

2ns(max_delay) - 3ns(output_delay) = -1ns;

And the arrived time is as follows:

3ns(input_delay) + tDELAY;

So tools think the constraints should be:

3ns(input_delay) + tDELAY < -1ns => tDELAY <-4ns;

But my thinking is that I want to constraint the max delay time is 2ns from ina to oub (tDELAY < 2ns), so, for that, I need to constraint the max_delay is 8ns;

It is right?

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May I ask what is the thinking here?

you have an input (ina) going direct to output (outb) through some comb. logic that receives a registered version of ina(call it ina_r).

So ina_r will get sampled at clock edge running every 10 ns yet you want ina to outb < 2ns???

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