About timing constraints of ‘in2out’ timing path

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Q: About timing constraints of‘in2out’ timing path

My design is as follows:

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In my design, there are three ports: clk(system clock), ina(input port), outb(output port). My constraints are as follows:

create_clock -period 10 -name my_clk [get_ports clk]

set_input_delay -max 3 -clock my_clk [get_ports ina]

set_ouput_delay -max 3 -clock my_clk [get_ports outa]

set_max_delay 2 -from ina -to outb

When Quartus tools analysis the 3rd timing path, the required time calculated as follows:

3(input_delay) + 3(output_delay) + 2(max_delay) + tdelay(com logic delay) <10(clock cycle)

But I want to constraint the delay less than 2ns from ‘ina’ to ‘outb’, I don’t know how to constraint the timing path, could you please give me some advise for this case?

Thanks

wuyu

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May I ask what is the thinking here?

you have an input (ina) going direct to output (outb) through some comb. logic that receives a registered version of ina(call it ina_r).

So ina_r will get sampled at clock edge running every 10 ns yet you want ina to outb < 2ns???