Forum Discussion
Altera_Forum
Honored Contributor
Honored ContributorAbout styles of writing FSM
Hi, I find many people on their blog suggest coding FSM as follow.
always @ (posedge clk or negedge rst_n)
if(!rst_n)
current_state <= IDLE;
else
current_state <= next_state;
alw...
Altera_ForumHonored Contributor
Honored Contributor --- Quote Start --- This is down to personal preference. It's highly unlikely that the final implementation will differ as a result of using the different styles. You might argue that a more verbose coding style is more explicit and therefore helps the tools digest your code - there may be some particular inferences that cause the tools difficulty. I don't personally subscribe to this point of view. More relevant (I think) is the comment made regarding a more verbose style - it's more prone to error. --- Quote End --- It is more a style comment. But while the 1 always style may be more prone to functional error, the 2 always style, with unregistered outputs, is prone to latches which wont be picked up in a functional simulation, and will only appear as synthesis warnings that many people ignore. This will then probably manifest as timing issues in the design which wont prove obvious to an inexperienced engineer. stick to the 1 always style - then you know you're always getting registered output.
