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Altera_Forum's avatar
Altera_Forum
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8 years ago

About My VHDL Task

Hi, as a beginner in VHDL, I like to hear comments and ideas from you. I have a task to do, my lecturer sent me a code but I couldn't find out. This's the code. -- library ieee; u...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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The reg table only has 16 elements. It does seem a design flaw to count only from 0 to 14, rather than 0 to 15. It cannot run until 20 because it would overflow the reg array.

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I didn't mean that. The prescaler should be meaning and adjusting the frequency. If it has ability to count to 20(such as), This situation will be changing the frequency. There should be a calculation why he has 16 elements.