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Altera_Forum
Honored Contributor
Honored ContributorAbout My VHDL Task
Hi, as a beginner in VHDL, I like to hear comments and ideas from you. I have a task to do, my lecturer sent me a code but I couldn't find out. This's the code. -- library ieee; u...
Altera_ForumHonored Contributor
Honored ContributorThe reg table only has 16 elements. It does seem a design flaw to count only from 0 to 14, rather than 0 to 15. It cannot run until 20 because it would overflow the reg array.
