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If you're talking about VHDL, then yes / can be synthesised if you use the numeric_std package, but it doesnt allow the pipelining that LPM_DIVIDE gives.
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Thank you,Tricky. I used Verilog HDL, can '/' be synthesised ?
My testbench codes is:
key_led key1
(
.clk(CLK),
.rst(RSTn),
.data_in(Dividend),
.data_v(Divisor),
.data_hun(Quotient),
.seg_out(Sout),
.bit_out(Bout),
.rem(Reminder)
);
always @(posedge CLK)
begin
# 10 Dividend = 123;
# 20 Divisor = 10;
end
endmodule
-------------------------------------------------------------
My source .v file is
module key_led(
clk,rst,seg_out,bit_out,data_in,data_v,data_hun,rem
);
input clk,rst;
output [7:0] bit_out,seg_out,data_hun,rem;
input [7:0] data_in ,data_v;
wire done_sig_hun,start_sig_hun;
wire done_sig_dec,start_sig_dec;
wire [7:0] data_dec,data_uni,data_dec_w;
reg [7:0] seg_out,bit_out;// Nixie tube driver ports
reg [15:0] scan_cnt;
wire dec_clk;
assign data_uni = data_in %10;
assign data_dec_w = data_in %100;
always@(data_hun)
begin
bit_out = 8'b1111_1110;
seg_out = data_hun;
end
mydiv dv_hun(.denom(data_in),.numer(data_v),.quotient(data_hun),.remain(rem));
endmodule
How to use LPM_DIVIDE from Quartus II ?
The picture is my waveform at modelsim.
Honored Contributor
