About Divide-By-50-Divider

Hi bros, I have a problem, and I'm very glad to receive your help. This is schematic of a Divide-By-50-Divider (I referred to The Flite Electronics FPGA/CPLD Trainer Experiment Manual), and I wanna convert it into Verilog code.

https://www.alteraforum.com/forum/attachment.php?attachmentid=6883

This is my Verilog code for Divide-By-50-Divider:

module div50 (Clko, Clkin);

input Clkin;

output Clko;

t_ff T0 (Y0, W16, Clkin, 1, 1);

t_ff T1 (Y1, W17, Clkin, 1, 1);

t_ff T2 (Y2, W18, Clkin, 1, 1);

t_ff T3 (Y3, W19, Clkin, 1, 1);

t_ff T4 (Y4, W13, Clkin, 1, 1);

t_ff T5 (Y5, W14, Clkin, 1, 1);

t_ff T6 (Y6, W15, Clkin, 1, 1);

and_2 A0 (W0, Y5, ~Y4);

and_4 A1 (W1, Y5, ~Y3, ~Y2, ~Y1);

and_2 A2 (W2, ~Y5, Y0);

and_3 A3 (Y5, ~Y4, Y0);

and_3 A4 (W4, ~Y5, Y1, Y0);

and_4 A5 (W5, Y5, ~Y4, Y1, Y0);

and_4 A6 (W6, ~Y5, Y2, Y1, Y0);

and_5 A7 (W7, Y5, ~Y4, Y2, Y1, Y0);

and_5 A8 (W8, ~Y5, Y3, Y2, Y1, Y0);

and_6 A9 (W9, Y5, ~Y4, Y3, Y2, Y1, Y0);

and_6 A10 (W10, ~Y5, Y4, Y3, Y2, Y1, Y0);

and_6 A11 (W11, Y7, Y4, ~Y3, ~Y2, ~Y1, Y0);

and_6 A12 (W12, ~Y5, Y4, Y3, ~Y2, ~Y1, ~Y0);

or_3 O0 (W16, W0, W1, ~Y5);

or_2 O1 (W17, W2, W3);

or_2 O2 (W18, W4, W5);

or_2 O3 (W19, W6, W7);

or_3 O4 (W13, W8, W9, W10);

or_2 O5 (W14, W10, W11);

or_2 O6 (W15, W11, W12);

assign Clko = Y6;

endmodule

I have check and have'nt detected any error here, but when I compiled this code by Quartus 9.1 sp2 Web Edition, I've got a messages:

Info: Elaborating entity "div50" for the top level hierarchy

Info: Elaborating entity "t_ff" for hierarchy "t_ff:T0"

Info: Elaborating entity "and_2" for hierarchy "and_2:A0"

Info: Elaborating entity "and_4" for hierarchy "and_4:A1"

Info: Elaborating entity "and_3" for hierarchy "and_3:A3"

Info: Elaborating entity "and_5" for hierarchy "and_5:A7"

Info: Elaborating entity "and_6" for hierarchy "and_6:A9"

Info: Elaborating entity "or_3" for hierarchy "or_3:O0"

Info: Elaborating entity "or_2" for hierarchy "or_2:O1"

Error: Net "Y5", which fans out to "and_6:A11|Y1", cannot be assigned more than one value

Error: Net is fed by "t_ff:T5|q"

Error: Net is fed by "and_3:A3|F"

Warning: 8 hierarchies have connectivity warnings - see the Connectivity Checks report folder

Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 28 warnings

Error: Peak virtual memory: 175 megabytes

Error: Processing ended: Mon Mar 04 10:33:30 2013

Error: Elapsed time: 00:00:01

Error: Total CPU time (on all processors): 00:00:01

Error: Quartus II Full Compilation was unsuccessful. 5 errors, 28 warnings

Anybody can help me, please?