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Altera_Forum
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13 years ago

About Divide-By-50-Divider

Hi bros, I have a problem, and I'm very glad to receive your help. This is schematic of a Divide-By-50-Divider (I referred to The Flite Electronics FPGA/CPLD Trainer Experiment Manual), and I wanna c...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
13 years ago

The error message tells you the problem and which two lines are causing it. I guess it's just a typo in

and_3 A3 (Y5, ~Y4, Y0);

Y5 shouldn't be connected as an output here.