--- Quote Start ---
process (clk,areset)
if (areset = '1') then
--reset signal to a known state
elsif (rising_edge(clk)) then
-- do some stuff
--- Quote End ---
The areset signal must be 'synchronized' to the 'clk'. This VHDL connects the signal to the asynchronous reset port of the FPGA registers. Those registers have a 'setup/hold' timing requirement with respect to the reset port.
The TimeQuest documentation discusses this.
I first read about it a while ago in some papers by Cliff Cummings at Sunburst design (he has lots of good advice). Read the two papers on resets (and the ones on FIFOs are good too):
http://www.sunburst-design.com/papers/ Cheers,
Dave
Honored Contributor
