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Change your habits. Place a reset synchronizer at the top-level of the design for
every different clock domain, i.e., don't have a port list with rstN, a_clk, b_clk on your lower-level components, have a_rstN, a_clk, b_rstN, b_clk. That way you have the synchronizers in one place. (SOPC Builder/Qsys will probably insert extra synchronizers).
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thankfully I only have one clock driving logic.
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It should analyze it via reset recovery analysis. But if you cut the path, then it'll ignore it. So it depends what you did in your .sdc file.
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My .sdc file is very short. the clock definitions. that Timequest derived from the PLL instantiation, SOPC builder generated assignments, and false path between my clock and altera internal JTAG clock.
KAZ, according to the RTL viewer, the decoder includes a register for it's input and then the decoding logic (a XOR not for each signal). anyway this signal are coming from the NIOS not IOs. I run the Timequst to the entire design, not for each block separately.
and as I said I only have one clock domain.
when I say asynchronous I mean that in the block VHDL code I have something like:
process (clk,areset)
if (areset = '1') then
--reset signal to a known state
elsif (rising_edge(clk)) then
-- do some stuff
I didn't mean that the signal itself is asynchronous to the design, apparently this kind of coding is appropriate, only for that kind of signals, and if I understand you correctly even then you recommend first registering the signal and then treat it as synchronous reset.
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