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Hi
It's strange though that Timequest didn't recognize the threat.
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Any timing analysis can only check destination registers when source signal changes are known. I mean if your signal is just an input(unregistered) then there is no path from its entry to its destination register to be analysed as signal transitions are undefined. This rule applies to any inputs thus for any project submodule, timing analysis will not check front end registers and for asynch reset it will find no paths for recovery/removal. The remedy is to register all inputs (at least temporarily for the sake of timing until integration adds input registers).
The io timing entries(set input delay) is the way to give that info for actual final inputs. However it does not apply to asynchronous reset which is best synchronised first to its clock domain then applied to the its dedicated register port.
Honored Contributor
