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I started to realize that after I posted my question. sometimes writing something down helps to organize the thoughts. :)
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Yep, I can appreciate that!
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I use asynchronous reset as a habit, It always looked more robust to me. I guess I should use only at the top of the design for hard reset from the board or from the PLL lock signal, not when it is sourced from combinatorial logic...
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Change your habits. Place a reset synchronizer at the top-level of the design for
every different clock domain, i.e., don't have a port list with rstN, a_clk, b_clk on your lower-level components, have a_rstN, a_clk, b_rstN, b_clk. That way you have the synchronizers in one place. (SOPC Builder/Qsys will probably insert extra synchronizers).
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It's strange though that Timequest didn't recognize the threat.
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It should analyze it via reset recovery analysis. But if you cut the path, then it'll ignore it. So it depends what you did in your .sdc file.
Cheers,
Dave
Honored Contributor
