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one of the function I use these discrete lines is as asynchronous reset to blocks of the design.
so far so good.
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No, not so good.
If you simulate the post-place-and-route design, you will probably see glitching on the combinatorially generated reset line.
Register the reset signal with the same clock as your NIOS system. This will ensure that there are no glitches on the reset line.
If the reset is going to another clock domain, you should then synchronize the reset there too; it can asynchronously assert, but synchronously deassert. Altera has examples showing how to correctly synchronize reset.
Cheers,
Dave
Honored Contributor
