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Altera_Forum's avatar
Altera_Forum
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11 years ago

A Question on SignalTap

I am monitoring a 14-bit DAC and a 14-bit ADC. The DAC outputs 1MHz samples from an NCO. The DAC output goes to an SMA

which then is looped back to an ADC. Sampling freq is 100 MHz which is also the SignalTap acquisition clock. Signaltap is in the simple

continuous mode. There are no triggers. Has a 4K buffer.

Once I start acquiring data the waveforms appears. However, there is a lot of jitter.

Is this because SignalTap acquires the 4K samples faster than the JTAG is downloading to the PC?

(Since the JTAG is much slower, then, some samples are being overwritten. So, by the time the samples are downloaded to the PC

the acquisition buffer has already filled.) Is that what is causing the jitter?

Thanks,

Swimteam

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    11 years ago

    Generally SignalTap is not a continuous capture. (I don't know if there's some way to do that, but I've never seen it). Basically it's running along and capturing data in memory, all synchronous and all 100% accurate, assuming it's in the same clock domain as your logic and your design met timing. When the trigger occurs, it stores however much data you wanted captured before the trigger and then fills up the rest post capture and downloads to your computer over JTAG, but it stops capturing on that trigger and won't recapture new data on top of it until you tell it to. So it should be accurate and the ?jitter? is from somewhere else.

    That's SignalTap's power, in that it gives bit-by-bit, cycle-by-cycle data that is accurate. Often that's so much information it's a pain to decipher, but it's all there.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    11 years ago

    Hi,

    I have on question too on Signal Tap II Logic Analyzer in Quartus 13.1. I am using 12-bit ADC for fetching data into my altera Sockit Cyclone V. The problem is I can see some data samples on some of the lvds_rx_port0 and on lvds_rx_port1 but i can't see Altera Pll Clock . Please have a look on attached picture and guide me what those data samples are and why i am unable to have Clock signal.

    Thanks in advance !

    Best regards,

    Shahbaz