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Honored Contributor
Honored ContributorA question about the asynchronous clear signal of dual clock FIFO
Hi, I used a MegaWizard generated dual clock FIFO in a design. FIFO width is 16 bits and its depth is 2048. The write and read clock of this FIFO is 90 MHz and 60 MHz respectively. Both of the...
Altera_ForumHonored Contributor
Honored ContributorIf you're not writing to the FIFO out of reset, then you can put a false path on that. (set_false_path -from [get_keepers {reset_register_or_port}] -to [get_keepers {*dc_fifo_hierarchy*}]
Also make sure you're not reading, or that read protection is on(which is on by default). The aclr can be very short, so one pulse should be fine.
