A question about parameterized structure between interface and module

This is exactly what a SystemVerilog interface is for.

interface# (int BITWIDTH_OF_SIG2) client_interface;
typedef struct packed {
    logic sig1;
    logic sig2;        // BITWIDTH_OF_SIG2 is the parameter that should be passed from client or server module.
} client_info_t;
client_info_t info;
modport client(output info);
modport server(input info);
endinterface
module server_module (
   ...
   client_interface.server client_port,
   ...
);
...  // access client_port.info as an input
endmodule
module client_module  (
    ...
    client_interface.client client_port,
    ...
);
 // ...  // access client_port.info as an output
endmodule