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Altera_Forum's avatar
Altera_Forum
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15 years ago

A High Impedence Shift Register

Hello all,

I'm attempting to modify my code of a serial in parallel out shift register. What I want is a shift register that has a high-impedance instead of a Low. So, for instance, a "normal" shift register would have 01000000 loaded onto it. But I need Z1ZZZZZZ. Here's my attempt: 

library ieee; 
use ieee.std_logic_1164.all; 
entity SerialInParallelOut is
	port(CLK, SI, Reset : in std_logic;
						POut : out std_logic_vector(29 downto 0));
end SerialInParallelOut;
architecture shift of SerialInParallelOut is
	signal tmp: std_logic_vector(POut'high downto POut'low);
	begin
		process(CLK,Reset)
			begin
			if Reset = '1' then
				tmp <= "ZZZZZZZZZZZZZZZZZZZZZZZZZZZZZZ";
			elsif rising_edge(CLK) then
				tmp <= tmp(Pout'high - 1 downto Pout'low) & SI;
			end if;
		end process;
	POut <= tmp;
end shift;

Note the reason I'm attempting to do this are explained in this thread. (http://alteraforums.com/forum/showthread.php?t=32424).

Unfortunately, I get a warning stating that Tri-state node(s) do not directly drive top-level pins. I understand what this warning means: it's stating that tri-state is only available at the output pins. But I'm not quite sure how to modify my code such that only the output pins would have tri-state.

26 Replies

  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    What I want is a shift register that has a high-impedance instead of a Low.

    --- Quote End ---

    A shift-register that contains 'Z' is not synthesizeable.

    What you need to design is a shift register that contains the output and output-enable values, and then drive those to tri-state buffers.

    Lets say Pout_out is the vector of output values, and Pout_oe is the vector of tri-state output-enable controls, then you can define your tri-stated output via something like: 

    
process(Pout_out, Pout_oe)
begin
    for i in 0 to POUT_WIDTH-1 loop
         Pout(i) <= 'Z' when (Pout_oe(i) = '0') else Pout_out(i);
    end loop;
end process;
    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    Thanks Dave. I've been thinking about this for some time and came up with this: 

    library ieee; 
use ieee.std_logic_1164.all; 
entity SerialInParallelOut is
	port(CLK, SI, Reset : in std_logic;
						POut : out std_logic_vector(29 downto 0));
end SerialInParallelOut;
architecture shift of SerialInParallelOut is
	signal tmp: std_logic_vector(POut'high downto POut'low);
	begin
		process(CLK,Reset)
			begin
			if Reset = '1' then
				tmp <= "000000000000000000000000000000";
			elsif rising_edge(CLK) then
				tmp <= tmp(Pout'high - 1 downto Pout'low) & SI;
			end if;
		end process;
		
	process(tmp)
	begin
		for i in 0 to POut'high loop
			POut(i) <= tmp(i) when tmp(i) = '1' else 'Z';
		end loop;
	end process;
end shift;

    I'm not sure if its correct logically. But I'm unable to compile it as well. It says

    error (10500): vhdl syntax error at serialinparallelout.vhd(25) near text "when"; expecting ";"

    I don't know why it wants a ; near when. Is there anything else that needs changing or will this work well for my purpores?

    My thought process was: I need to have an internal buffer, which has 0s and 1s. But when outputting that buffer, I need to basically replace '0' with 'Z'. Am I correct?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    You can't use assignments with 'when' inside a process. You need to use if/else instead, and your code should compile.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    You can't use assignments with 'when' inside a process. You need to use if/else instead, and your code should compile.

    --- Quote End ---

    Thank you. And does it look logical and good code to you otherwise?
  • Altera_Forum's avatar
    Altera_Forum
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    15 years ago

    --- Quote Start ---

    And does it look logical and good code to you otherwise?

    --- Quote End ---

    Although this may seem like saying the same thing, the synthesis tool really wants to see the tri-state the way I first gave it to you, i.e., 

    
Pout(i) <= 'Z' when (tmp(i) = '0') else tmp(i);
    Recent versions of the tools might not care, but this is how tools used to need the statement to synthesize to only a tri-state buffer.

    You realize of course that this will take your output pins and drive them high only. Is that what you want?

    If you wanted an open-drain type function, I would expect to use the weak pull-ups for a high (via the weak-pullup enable constraint), and then use the tri-state buffer to generate a low, i.e., 

    
Pout(i) <= 'Z' when (tmp(i) = '0') else '0';

    Create a Modelsim simulation of your logic. You can create a weak pull-up in the simulation by including the statement 

    
Pout <= (others => 'H');

    in the testbench.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Dave,

    My goal is to tri-state the outputs which aren't active. I will have pull up/down resistors on every output which give them a default state. I haven't yet decided whether to use pull up or downs. I think eventually I will go with pull ups if I can get a 4-layer board manufactured. It will make laying the pull up resistor quite easy. If I stay with 2-layer, I may stick with pull down as my bottom layer is ground. One thing that I am sort of concerned about - if I use a pull down, will it interfere with the programmable pull up resistor? I'm not using that on purpose.

    Based upon Daixiwen suggestion, I changed my code to a If... else and here's what it looks now. I couldn't get the when statement to compile. 

    
library ieee; 
use ieee.std_logic_1164.all; 
entity SerialInParallelOut is
	port(CLK, SI, Reset : in std_logic;
						POut : out std_logic_vector(29 downto 0));
end SerialInParallelOut;
architecture shift of SerialInParallelOut is
	signal tmp: std_logic_vector(POut'high downto POut'low);
	begin
		process(CLK,Reset)
			begin
			if Reset = '1' then
				tmp <= "000000000000000000000000000000";
			elsif rising_edge(CLK) then
				tmp <= tmp(Pout'high - 1 downto Pout'low) & SI;
			end if;
		end process;
		
	process(tmp)
	begin
		for i in 0 to POut'high loop
			if tmp(i) = '0' then
				POut(i) <= 'Z';
			else
				POut(i) <= '1';
			end if;
		end loop;
	end process;
end shift;

    This does seem to work in Model Sim but as you know better, I thought I should post it here and ask your advice regarding this. I notice you again mentioned the when statement. Unfortunately, I can't get that to compile - maybe I'm doing something wrong? But even copy pasting your code, changing variable names didn't work.

    You mention a weak pull up enable constraint. Pardon my ignorance, but I'm not quite sure what you're referring to. Perhaps some background maybe useful: the shift register's parallel out will be connected to wires that it's supposed to test for short circuits. The parallel out will basically have a "walking one" test vector loaded onto it. The wire that was being tested had a '1' and the other had a '0' on it. If they're shorted, the output pins would fight each other because they'd be trying to drive the same signal. But if I instead make the inactive pin high impedance, it'll be inactive and this situation won't arrive. At the same time, the wire will have a default value due to the pull up/down resistor.

    here's a link to another thread which has more info. if you desire. (http://www.alteraforum.com/forum/showthread.php?t=32424) I hope you can see my requirement more clearly now.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    My goal is to tri-state the outputs which aren't active.

    --- Quote End ---

    Right, but what is the active state supposed to be? Driven high or low?

    --- Quote Start ---

    I will have pull up/down resistors on every output which give them a default state. I haven't yet decided whether to use pull up or downs. I think eventually I will go with pull ups if I can get a 4-layer board manufactured. It will make laying the pull up resistor quite easy.

    --- Quote End ---

    Can you just use the weak pull-ups on the FPGA?

    --- Quote Start ---

    One thing that I am sort of concerned about - if I use a pull down, will it interfere with the programmable pull up resistor? I'm not using that on purpose.

    --- Quote End ---

    No, you just have to use a pull-down that is stronger (smaller resistance) than the pull-up (which is ~20kOhm I think).

    --- Quote Start ---

    Based upon Daixiwen suggestion, I changed my code to a If... else and here's what it looks now. I couldn't get the when statement to compile.

    --- Quote End ---

    Sorry about that; the when statement works inside a generate loop, but not inside a process loop. You've got the code right now. Here's a couple of style changes ... 

    
library ieee; 
use ieee.std_logic_1164.all; 
entity SerialInParallelOut is
    port(CLK, SI, Reset : in std_logic;
                        POut : out std_logic_vector(29 downto 0));
end SerialInParallelOut;
architecture shift of SerialInParallelOut is
    constant WIDTH : integer := 30;
    signal tmp: std_logic_vector(POut'high downto POut'low);
begin
      process(CLK,Reset)
            begin
            if Reset = '1' then
                tmp <= (others => '0');
            elsif rising_edge(CLK) then
                tmp <= tmp(WIDTH - 2 downto 0) & SI;
            end if;
        end process;
        
    process(tmp)
    begin
        for i in 0 to WIDTH-1 loop
            if tmp(i) = '0' then
                POut(i) <= 'Z';
            else
                POut(i) <= '1';
            end if;
        end loop;
    end process;
end shift;

    --- Quote Start ---

    You mention a weak pull up enable constraint. Pardon my ignorance, but I'm not quite sure what you're referring to.

    --- Quote End ---

    Given a pin on the FPGA called foo, you can enable the weak pull-up using the Tcl command 

    
set_instance_assignment -name WEAK_PULL_UP_RESISTOR ON -to foo
    See p720-721

    http://www.altera.com/literature/manual/mnl_qsf_reference.pdf

    --- Quote Start ---

    Perhaps some background maybe useful: the shift register's parallel out will be connected to wires that it's supposed to test for short circuits. The parallel out will basically have a "walking one" test vector loaded onto it. The wire that was being tested had a '1' and the other had a '0' on it. If they're shorted, the output pins would fight each other because they'd be trying to drive the same signal. But if I instead make the inactive pin high impedance, it'll be inactive and this situation won't arrive. At the same time, the wire will have a default value due to the pull up/down resistor.

    --- Quote End ---

    So why not use the pull-up on one end, and the shift-register driving a 0 on the other.

    Cheers,

    Dave
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Thanks!

    Regarding what's the active state - I already wrote the code for an active state of High. Let's go with 0 this time so that I know the code both cases. I know that I need a pull up in this case and I assume I just need to change the if statement in my code to this: 

    for i in 0 to WIDTH-1 loop
            if tmp(i) = '1' then
                POut(i) <= 'Z';
            else
                POut(i) <= '0';
            end if;
           end loop;

    and just change 
    tmp <= (others => '0');
    to 
    tmp <= (others => '1');
    and I'll be set.

    I think I'll stick with this because I may need a weaker pulling resistance. This is because a short circuit can end up causing one pin to drive quite a few wires (100 max) and if the resistance is too low, it will pull a more than the rated current of a pin. With about 27K resistance, I think the current draw will be just 12mA, when its driving 100 wires. I think thats within the drive capability of a pin.

    PS: I'm not using an FPGA, exactly. I'm using the Max V CPLD.
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    --- Quote Start ---

    Thank you. And does it look logical and good code to you otherwise?

    --- Quote End ---

    Hello could you tell me how to set a current file(there are some vhdl files but how can I compile the file I want )?Thank you!!!
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    15 years ago

    Hello could you tell me how to set a current file(there are some vhdl files but how can I compile the file I want )?Thank you!!!