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Altera_Forum
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18 years ago

7.2sp1 cant produce working sof

I am using a CII dev board with Q7.2sp1 web edition. The PLL in my Q7.2 niosII project seemed to stop working after some unrelated mods, so I installed Q7.2sp1 thinking it might help. I created...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
18 years ago

Hello,

I tried with V7.2 (I didn't yet install SP1) without doing pin assigments, so the fitter picked input and output pins. From the Pin-Out File, the "design" looks functional.

pin_name1 : 57 : output : 3.3-V LVTTL : : 4 : N

pin_name : 58 : input : 3.3-V LVTTL : : 4 : N

GND* : 59 : : : : 4 :

GND* : 60 : : : : 4 :

Also when assigning pin locations explicitely in Pin Planner, anything seems to be correct. I don't think there is a difference between HDL or BDF input. Could it be that SP1 behaves different?

Regards,

Frank