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Altera_Forum's avatar
Altera_Forum
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12 years ago

4bit siso shift register

I used the following code for 4bit siso shift register.

Signal temp : std_logic_vector( 3downtown 0);

begin

process

begin

if(rising_edge(clk)) then

temp(3 downtown 1)<=temp(2 downto 0);

temp(0)<=si;

end if;

end process;

so<=temp(3);

end behavioural;

I used the following testbench code.

clk<= '0';

si<='1';

wait for 100ns;

clk<= '1';

si<='1';

wait for 100ns;

But after stimulation its shows that so is undefined i.e

a red bar is shown....

Pls help......

6 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    You only show a single clock in the testbench code. It will take 4 clocks for si to propogate to so.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    clk<= '0';

    si<='1';

    wait for 100ns;

    clk<= '1';

    si<='1';

    wait for 100ns;

    clk<= '0';

    si<='1';

    wait for 100ns;

    clk<= '1';

    si<='1';

    wait for 100ns;

    clk<= '0';

    si<='1';

    wait for 100ns;

    clk<= '1';

    si<='1';

    wait for 100ns;

    clk<= '0';

    si<='1';

    wait for 100ns;

    clk<= '1';

    si<='1';

    wait for 100ns;

    I have used the above coding.....

    Even if I use 4 clocks its still shows the red bar
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    did you try to initialize temp(3 downto 0) to an initial value? If not you need at least 4 clock edges to get "so" "green"

    if "red" it would be that you never put anything on it...