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Altera_Forum
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11 years ago

32-bit adder Carry Look-ahead

Hi, I am new to Verilog and I am trying to implement a 32-bit adder Carry Look-ahead, but the output is incorrect. I included the simulation in ModelSim and my verilog code. https://www.alterafo...
Altera_Forum's avatar
Altera_Forum
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10 years ago

Some advice, if you want synthesizable logic I recommend avoiding delays in your RTL. That code will simulate fine but if you compile it for an FPGA you might end up surprised by the way it behaves in actual hardware.