20ns pulse generation at rising edge

Hello,

I'd like to generate a 20ns high signal at the rising edge of another (clocked, 330ns) signal.

Formally, they are a 50MHz clock and a 3MHz clock.

Right now, I am stuck at the very beginnin' of this task. I mean, I found many codes that can generate a pulse if a rising edge condition is meet. Anyway, there's no control on the pulse duration.

I was thinking of a signal locked at the rising edge of the 3Mhz signal to trigger a state machine clocked @50Mhz. My problem is that I can't figure out how to deassert the trigger signal, since it will deassert on the next rising edge of the control signal.

Here is a (wrong) code I made since now - i didn't include resets here to make it easibily readable.

I don't expect a solution, or it to work. I'd like just a hint.

--- Quote Start ---

always@(posedge 3Mhz_signa)

begin

up<=1;

end

always@(posedge 50Mhz_signal) begin

case(fsm)

0:begin;

data_out<=0;

if up(fsm<=1);

end

1:begin;

data_out<=1;

fsm<=0;

end

endcase

endmodule

--- Quote End ---

how can i deassert "up" signal after 20ns, being locked to posedge 3Mhz clk?

I was thinking of a sort of "feedback", but still not ideas.

EDIT:

i seems like I didn't search enough on google.

I found out this (http://www.oldcrows.net/~patchell/iparchive/oneshot.v) that's exactly what I needed.

Basically, feedback was the right way.

I've a long way to proper learn coding.