2 top level design entity

I am designing two different symbols that i need for particular design.

And i have both raw circuit for the symbols in the same project,which one should i make the top level design entity,cos the circuit i design using the symbols won't compile without the raw or original circuit that forms the symbols.

Both circuit and symbols are different modules that cannot be join together cos i am using there symbols to cascade.

When i compile the cascaded symbols to form the new circuit without the original circuits,i get the follow error message;

Error: Node instance "inst" instantiates undefined entity "CSTEP1"

Error: Node instance "inst2" instantiates undefined entity "CSTEP1"

Error: Node instance "inst1" instantiates undefined entity "STEP2ADDER"

Error: Quartus II Analysis & Synthesis was unsuccessful. 3 errors, 0 warnings

Error: Peak virtual memory: 236 megabytes

Error: Processing ended: Thu Mar 03 07:14:47 2011

Error: Elapsed time: 00:00:03

Error: Total CPU time (on all processors): 00:00:02

Error: Quartus II Full Compilation was unsuccessful. 5 errors, 0 warnings

So how do i make both top level design,or is using one the correct thing to do?