2 hold checks - why?

I made some reading of TimeQuest and my understanding is this:

First for setup time(Tsu) it defines a launch edge as the closest previous to a latch edge. This is the easy bit.

For hold time(Th) it makes sure that every launch edge drives its next latch edge.(remember the central idea is that every launch edge(source flip) must drive its next latch edge(destination flip) but this has to be designed carefully through delays by fitter and then checked by TimeQuest, failure could occur resulting in occasional edge slips when a launch edge loses track of its latch edge).

The discussion is centred on flipflop chains, each flip sourcing the next flip. It is purely of interest to Altera chip architects rather than fpga field engineers. However basic background is useful. But I don't quite see why all those strings of equations of data delay/clk delay put in this document as it is purely a headache for the architects and not the poor field engineers. Surely there is some commercial impact on the vulnerables...

edit:

Altera architects depend very much on Fmax to control Tsu. But for (Th) they depend on their internal design of data/clk delays to keep Th right until the field designer comes forward and gates the clks certainly leading to clk skew if it is not put back on those global fast lines