What document are you looking at? Note that for a given path TimeQuest only analyzes the most restrictive hold requirement, since if it passes that, it passes any less restrictive checks. So every launch edge must make sure it passes its own hold requirement. The quote "well you have to check the current launch against the previous latch and the current latch against the next launch" can be re-interpreted so the latter part is just a check of subsequent launch edges to subsequent latch edges. I personally would say there are more than 2 hold checks. Think of an 8ns clock feeding a 10ns clock. The first rising edge at time 0 has a hold requirement of 0ns to the latch edge at time 0ns(assuming no MCs). This happens to be the most restrictive hold requirement. But the next launch edge at time 8ns has a -8ns hold requirement to the latch edge at time 0ns. The launch at time 16ns has a -6ns hold requirement to the latch at time 10ns. There is also a -4ns and -2ns hold requirement before the pattern starts repeating. (These are edge aligned so the first requirement happened to be the most restrictive. But, for example, on a setup requirement where a 10ns clock feeds an 8ns clock, the most restrictive setup will be 2ns, with a launch at time 30ns and latch at time 32ns). And if the clocks even stranger frequencies, it gets worse, to the point I can't easily figure it out(i.e. when a 4.567ns clock feeds a 7.890ns clock.) Of course, these should just be considered asynchronous. But the directions should show how TQ analyzes them.
(FYI, source synch DDR is about as painful as it gets, at least to do correctly. I posted a document with examples that hopefully helps, in case you're interested.)