16 bit vhdl multiplication

Here you go:

signal a : unsigned(31 downto 0);
signal b,c : unsigned(15 downto 0);
a <= b *c;

sir can you please post the full program for 16 BIT MULTIPLICATION IN VHDL, i find it tough creating the code comparing to verilog ..please sir ..i am eagerly waiting for your post ..,need to complete this task as early as possible,

This is the full program. the * operator is a perfectly valid way of doing a multiplication in VHDL.

here you go - a 16 bit multiplier module:

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
entity mult_16 is
port (
  a,b : in  unsigned(15 downto 0);
  c   : out unsigned(31 downto 0)
);
end entity mult_16
architecture rtl of mult_16 is
begin
  c <= a * b;
  
end architecture rtl;

sir the one you hav posted is a simple code..,i expect a 16 bit BINARY MULTIPLICATION code..,plzz help me sir

But this code does do 16 bit multiplication. Why would I do anything else? Its worked fine for me for over 8 years (and for many other people for many years before that).

@pop parithi - I'm only a VHDL newbie but I assure you that the answer really is as simple as shown above.