Altera_Forum
Honored Contributor
Honored Contributor.sdc file: TimeQuest Timing Analyzer (quartus II)
Any good tutorial with examples to setup the .sdc file? Besides, is it possible to generate the Verilog files based on a schematic file (.bdf)?
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Altera_ForumHonored Contributor
Honored ContributorU can search at www.altera.com, there are some document on the timing analysis, which should have note on the sdc.
Foe generate the verilog, after u compile the design using Quartus II, u can generate verilong netlist using netlist writer.
