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Altera_Forum
Honored Contributor
Honored Contributor*** Read Me ***
Post only questions about VHDL coding in here. Also if you are working on school projects you should not ask others to do you course work for you (your professor may be watching...)
Altera_ForumHonored Contributor
Honored ContributorI just tried and I saw the same thing until I saved the .vhd file and had it added to the project, then the symbol generator option was not greyed out.
By the way, I don't recommend posting to this thread, it's meant to remind people of the rules. Instead create new threads so that people will notice it.
