.JIC file Generation

You are a little confused. You can program the epcs using 3 different methods:

1 - Active Serial programming - This is not what you are trying to do so we'll skip it.

2 - JTAG Indirect Programming (JIC file) - If you are going to do this, then you use the Quartus convert programming file utility to directly create a JIC file from your SOF and any other data you need. You do not use the nios tools at all in this case.

3 - NIOS II flash programmer - This is my preferred method and it's also the fastest. you use the sof2flash and elf2flash utilities just as you have done to create ".flash" files for both your firmware and software images. Before you can program the EPCS you must program the FPGA with a SOF file containing your NIOS processor and an EPCS flash controller for this method to work. You can do this from the command line using the "quartus_pgm" command. Then At this point you just use the nios2-flash-programmer command to program the ".flash" files into the EPCS.

Finaly I got the Clue how to get my NIOS into a jic for our factory ...

It took quite a while and I'm wondering why so few people have this issue ... anyway ...

1.) Start the flash-programmer in the NIOS-IDE (we need the flash file, you may just run the sh-script as well ...)

2.) Start nios command shell and switch to the Release Directory

3.) Copy the fpga.flash and the software.flash -srec into one single srec-file ...

[NiosII EDS]$cat Quartus_Project_Revison.flash >merge.flash

[NiosII EDS]$cat epcs_controller.flash >>merge.flash

3.) convert it to intel-hex for programming file convertor in Quartus

[NiosII EDS]$ nios2-elf-objcopy.exe -I srec -O ihex -v emerge.flash merge.hex

4.) Use Quartus -> File -> Convert Programming File ...

select output: *.jic , select your epsc, outputfilename,

select flash-loader for your device

remove sof-entry

add hex file (merge.hex, absolute)

Generate ...

5.)programm with the quartus-programmer :-)

PS:

Girls&Boys from Altera: INCLUDE THIS SCRIPT SOMEWHERE IN 9.1 !!!

I would like to automaticaly integrate this into the Build/Flash Progress, ...

I did some script to help me - Here, my inputs are: .sof file and .elf file.

After this, script will generate .hex file.

With this I NEED to use converter from altera (PLS ALTERA BOYS: CREATE A COMMAND LINE FOR .JIC GENERATION). But, this script help me a little.

(I attached!)

# !/bin/bash

sof=""

elf=""

hex=""

# Processing arguments

if [ $# -lt 3 ]; then

echo "Usage: jicgen -s <hardware.sof> -e <firmware.elf> -o <out_file.hex>"

echo "-s <hardware.sof> - Quartus Logic file"

echo "-e <firmware.elf> - Firmware NIOS generated file"

echo "-o <out_file.hex> - hex output file name"

echo

exit

fi

while [ $# -gt 0 ]

do

case $1

in

-s)

sof=$2

shift 2

;;

-e)

elf=$2

shift 2

;;

-o)

hex=$2

shift 2

;;

*)

echo "Usage: jicgen -s <hardware.sof> -e <firmware.sof> -o <out_file.hex>"

echo "-s <hardware.sof> - Quartus Logic file"

echo "-e <firmware.elf> - Firmware NIOS generated file"

echo "-o <out_file.hex> - hex output file name"

echo

shift 1

;;

esac

done

# Commands

echo "Converting SOF file..."

sof2flash --epcs --input=$sof --output=hw.flash --quiet

echo

echo "Converting ELF file..."

elf2flash --epcs --after=hw.flash --input=$elf --output=sw.flash

echo

echo "Creating HEX file..."

cp hw.flash hw_sw.flash

cat sw.flash >> hw_sw.flash

nios2-elf-objcopy --input-target srec --output-target ihex hw_sw.flash $hex

echo

Hi,

1. Do "File -> Convert Programming Files...", setup the conversion parameters the way you want and after that do "Save Conversion Setup..." to save them to a .cof file.

2. Save the next TCL script as "generate_jic_programming_file.tcl". Edit the script to replace "your_projectname_here.cof" with the name of the .cof file that you previously saved.

set module 
 
if  {
 
 #  Include commands here that are run after the assember
      post_message "Running after assembler"
      set cmd "quartus_cpf -c your_projectname_here.cof"
 
     #  If the command can't be run, return an error.
      if {  } {
            return -code error $input
  }
}
 

3. Add this to the Quartus settings file (.qsf):

set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:generate_jic_programming_file.tcl"

Now a .jic file will automatically be generated after assembly, no need to run scripts from the command line :)

--- Quote Start ---

Hi,

Here is the tcl script that I use to generate a .jic file automatically after assembly.

set module 
 
if  {
 
 #  Include commands here that are run after the assember
      post_message "Running after assembler"
      set cmd "quartus_cpf -c your_projectname_here.cof"
 
     #  If the command can't be run, return an error.
      if {  } {
            return -code error $input
  }
}
 

Just save it as "generate_jic_programming_file.tcl" and add this to the Quartus settings file (.qsf):

set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:generate_jic_programming_file.tcl"

And you should save your "Convert Programming files" settings in a .cof file. That file will be used by the script

--- Quote End ---

hi,

What's .cof file?!

i tried it amilcar's way but it seems to be not working. i have looked up in the quartus manual and tried it different ways but in vain. moreover whats bothering me is it doesnt even generate an error as it is supposed to be. can anyone provide some insight into this?

Thanks

Hemanth

1. Can you post the contents of your .cof file ?

2. Did you save the "generate_jic_programming_file.tcl" in the the same directory as the .cof and .qsf file ?

3. Did you edit your .qsf file ?

Hi amilcar,

--- Quote Start ---

1. Can you post the contents of your .cof file ?

--- Quote End ---

Contents of .cof file :

<?xml version="1.0" encoding="US-ASCII" standalone="yes"?>

<cof>

<eprom_name>EPCS64</eprom_name>

<flash_loader_device>EP4CE75</flash_loader_device>

<output_filename>Project_qout/FDC285M_GVI__20150210_090108.jic</output_filename>

<n_pages>1</n_pages>

<width>1</width>

<mode>7</mode>

<sof_data>

<user_name>Page_0</user_name>

<page_flags>1</page_flags>

<bit0>

<sof_filename>Project_qout/FDC_285M_GVI.sof</sof_filename>

</bit0>

</sof_data>

<version>5</version>

<create_cvp_file>0</create_cvp_file>

<auto_create_rpd>0</auto_create_rpd>

<options>

<map_file>1</map_file>

</options>

</cof>

--- Quote Start ---

2. Did you save the "generate_jic_programming_file.tcl" in the the same directory as the .cof and .qsf file ?

--- Quote End ---

Have saved it as jic_generator.tcl. The .tcl file is in the same directory as the .cof and .qsf files. However the .jic and .sof files are placed in another directory Project_qout as indicated by the .cof file.

--- Quote Start ---

3. Did you edit your .qsf file ?

--- Quote End ---

Yes I did.

set_global_assignment -name POST_MODULE_SCRIPT_FILE "quartus_sh:jic_generator.tcl"

This is the command I used in the .qsf file and in the TCL file has set a conditional epxression to analysis and synthesis step for testing purposes.

Tcl code :

set module [lindex $quartus(args) 0]

if [string match "quartus_map" $module] {# Generating .jic file based on .cof file

set cmd "quartus_cpf -c output_file.cof"

post_message "Generated .jic file with date and time"

# If the command can't be run, return an error.

if { [catch {open "|$cmd"} input] } {

return -code error $input

}

}

Note: Forgot to mention earlier but I am using Quartus II 64-bit version 13.1.2