哈囉大家好，我想問如何在Quartus II上產生傳播延遲，使用verilog #10寫法在編譯時會被忽略，請問有甚麼做法可以解決這個問題呢?

Propagation delays in Verilog like #10 are non-synthesizable and Quartus ignores delays coded in Verilog. If you really need to introduce a delay in a particular logic net, you will have to use buffers (ALTBUFF) components and specify the delay type. Another method of introducing delays could be via pipe-lining. Add a register in the circuit path and try getting the delay to the exact value needed.