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xuanzi
New Contributor
5 years ago加法器进位链
大家好,我最近用加法器构造进位链,出来的波形可以看到进位链没有形成,我想请问一下,如何让fpga中的LE工作在算术模式下,在我的程序中,查看底层,好像没有使用cin到cout,而是使用查找表,我想问一下怎么设置才能使用LE的进位链;我还想问一下,如何设置quartus软件,让它不优化我的电路。
KhaiChein_Y_Intel
Regular Contributor
5 years agoHi,
Can you check CARRY_SUM primitive is something you are looking for?
Verilog instantiation: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/prim/prim_file_carry_sum_d1405e205.htm
VHDL instantiation: https://www.intel.com/content/www/us/en/programmable/quartushelp/current/index.htm#hdl/prim/prim_file_carry_sum_d1405e216.htm
Thanks
Best regards,
KhaiY