writing vhdl code in nios ii processor

Hi, you can post your code within [ code] balises

(just a detail : std_logic_unsigned is NOT an IEEE package, but you can use it)

Your code is .... good for Halloween :-)

for the process, you want a synchronous process so write

process(reset, clk) -- nothing else
   -- variables if any
begin
   if reset = '1' then
      -- asynchronous variables and signals initializations here
   elsif rising_edge(clk) then
      ...
   end if;
end process;

You should name "re_n" and "we_n" since they are active low.

You inferred a RAM... it is just an internal RAM to your counter, that will be difficult to read from QSYS

What's happen

You inferred unwanted(?) delay : ram(waddr) ----> count ----> q. So you q is assigned after 2 clocks.

All is quite confused.

------------------

I suggest(only suggest) you to write a simple counter like this

process(reset, clk) -- nothing else
begin
   if reset = '1' then
      count <= 0; -- if count is integer with range 0 to 9
   elsif rising_edge(clk) then
      if  count < 9 then
            count <= count +1;
      else
            count <= 0;
      end if;
   end if;
end process;

and then connect the "count" signal to a PIO for QSYS.

In software, just read the PIO : IORD_ALTERA_AVALON_PIO_DATA(PIO_COUNTER);