write array of a data to sdram from nios using IOWR

When accessing memory that the is used for code with the cache bypassing macros you have to be careful of cache coherency issues. This is usually easier to explain with an example so here goes:

1) Nios is running some code that allocated a buffer using malloc

2) Code writes some temporary data to the buffer from step# 1

3) Code frees the buffer that was allocated in step# 1

4) Code malloc some more memory and happens to get the same memory as step# 1

5) Code attempts to perform cache bypassing writes to the buffer from step# 4, you now have a cache coherency issue because memory location being written to is also cached

To make sure it's safe to perform cache bypassing accesses to the buffer that may be previously cached you should flush those locations first. But it's probably more efficient to write those locations without using cache bypassing macros then flush them out after, especially if the latency between the Nios data master and memory is high.

If you are wondering why that example is a cache coherency problem, image in step 5 your cache bypassing access was allowed to go through. Eventually the cache line that maps to that location is going to get evicted and overwrite what you previously wrote to memory.