Why overwrite/reset the complete edge register in a PIO ISR?

Hello,

Refering to the Nios 2 software handbook (code below), why overwrite *edge_capture_ptr completely and clear the entire edge capture register with IOWR_ALTERA_AVALON_PIO_EDGE_CAP systematically?

Let's say that there are 2 buttons for this PIO. If two buttons are activated very close to each other, wouldn't the second ISR call overwrite *edge_capture_ptr? So if the program was slightly busy doing something else in the mean time, it would miss the first button. Why not do a logical OR with the current value obtained with IORD_ALTERA_AVALON_PIO_EDGE_CAP and let the program clear the corresponding bit of *edge_capture_ptr when it has done what it is supposed to do.

With the IOWR operation: why not just reset the one edge that was detected instead of doing a blanket reset?

Thanks!

Bertrand

#include "system.h"
#include "altera_avalon_pio_regs.h"
#include "alt_types.h"
#ifdef ALT_ENHANCED_INTERRUPT_API_PRESENT
static void handle_button_interrupts(void* context)
#else
static void handle_button_interrupts(void* context, alt_u32 id)
#endif
{
/* Cast context to edge_capture's type. It is important that this
be declared volatile to avoid unwanted compiler optimization. */
volatile int* edge_capture_ptr = (volatile int*) context;
/*
* Read the edge capture register on the button PIO.
* Store value.
*/
*edge_capture_ptr =
IORD_ALTERA_AVALON_PIO_EDGE_CAP(BUTTON_PIO_BASE);
/* Write to the edge capture register to reset it. */
IOWR_ALTERA_AVALON_PIO_EDGE_CAP(BUTTON_PIO_BASE, 0);
/* Read the PIO to delay ISR exit. This is done to prevent a
spurious interrupt in systems with high processor -> pio
latency and fast interrupts. */
IORD_ALTERA_AVALON_PIO_EDGE_CAP(BUTTON_PIO_BASE);
}