Altera_Forum
Honored Contributor
Honored ContributorWhy is Nios2 data chache line so short?
In Nios2 Processor Handbook I'd noticed tha there is only one word per data chache line.
Why had altera designed that ? In my mind the data cache would slow data traffic severity, because the cpu data master isn't latency-aware. It's that? I'm really mixed ! Maybe we can design a own's data cache port? Had Anybody do it?
