What is different between create simulation model and create testbench system in Qsys

Thanks all.

But I kind of confuse on this BFM simulation example

https://www.altera.com/support/support-resources/design-examples/design-software/qsys/exm-hps-axi-bfm.html

From what I know, in Qsys, if we choose to create testbench system option, then Qsys will create testbench system and connects the exported top-level interfaces from your system to Bus Function Models (BFMs). In this design, the exported surfaces is just the clock and reset. Hence, the top level testbench system will instantiate with clock and reset BFM. But, may i know how the HPS BFM model is included in the top level testbench since it does not exported to the top level interfaces in Qsys and Qsys will not instantiate the HPS BFM to the testbench.