Forum Discussion
We have only seen this on EMAC0. Running the same traffic into EMAC1 has never shown an issue, but it was not a terribly robust test. It's so easy to se this on EMAC0 that after trying for an hour on EMAC1 we gave up. And to be clear, we see this most easily by sending small packets (100 bytes) at high rates. "Normal" sized packets and typical rates has no problems.
The "solution" seems to be to set the DFF bit in the DMA operation mode register (0xff70[13]018). The documentation on this is unclear as to what it really does ("When this bit is set, the Rx DMA does not flush any frames because of the unavailability of receive descriptors or buffers as it does normally when this bit is reset.") but the problem is gone when we set it. We see no new bad behavior, but since it's not clear what flushing the DMA means/does, we don't know what lurks, ahead.
Anyone know what this bit really does, internally?