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Dzar's avatar
Dzar
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

What could explain a packet getting stuck in the HPS MAC on RX?

I am using a Cyclone V with dual-Arm processors in an SOC design where we use the HPS MAC to receive packets from a server. We have seen a problem where, using high packet-per-second rates, we see th...
Dzar's avatar
Dzar
Icon for Occasional Contributor rankOccasional Contributor
7 years ago

I have an update. After doing a run, I check the debug register (0xff700024 for EMAC0) and see that when it's zero, there is no stuck packet and things work as expected. But when it's non-zero, it's always 0x00000120 which indicates that a) The FIFO is not empty and b) the RX state is "receiving frame data."

But at this point, I'm not sending anything. There is nothing on the wire (I use Wireshark to confirm this). The register will not change no matter how long I wait.

So... what could cause the RX state machine to hang like this? It seems as though it doesn't see the EOF.